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Code:

IRIX Release 6.5 IP35 HUALALAI
Copyright 1987-2006 Silicon Graphics, Inc. All Rights Reserved.
Last login: Wed Mar  8 11:33:37 EST 2023 on ttyd1
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(   )                          (   )          (   )           .-.
| | .-.    ___  ___    .---.   | |    .---.   | |    .---.  ( __)
| |/   \  (   )(   )  / .-, \  | |   / .-, \  | |   / .-, \ (''")
|  .-. .   | |  | |  (__) ; |  | |  (__) ; |  | |  (__) ; |  | |
| |  | |   | |  | |    .'`  |  | |    .'`  |  | |    .'`  |  | |
| |  | |   | |  | |   / .'| |  | |   / .'| |  | |   / .'| |  | |
| |  | |   | |  | |  | /  | |  | |  | /  | |  | |  | /  | |  | |
| |  | |   | |  ; '  ; |  ; |  | |  ; |  ; |  | |  ; |  ; |  | |
| |  | |   ' `-'  /  ' `-'  |  | |  ' `-'  |  | |  ' `-'  |  | |
(___)(___)   '.__.'   `.__.'_. (___) `.__.'_. (___) `.__.'_. (___)


HUALALAI 1# hinv
8 700 MHZ IP35 Processors
CPU: MIPS R16000 Processor Chip Revision: 2.1
FPU: MIPS R16010 Floating Point Chip Revision: 2.1
Main memory size: 6144 Mbytes
Instruction cache size: 32 Kbytes
Data cache size: 32 Kbytes
Secondary unified instruction/data cache size: 4 Mbytes
Integral SCSI controller 4: Version SAS/SATA LS1068
  Disk drive: unit 0 on SCSI controller 4 (XVM Local Disk) (primary path)
  Disk drive: unit 1 on SCSI controller 4 (XVM Local Disk) (primary path)
Integral SCSI controller 2: Version IDE (ATA/ATAPI) IOC4
  CDROM: unit 0 on SCSI controller 2
Integral SCSI controller 5: Version Fibre Channel QL2200A
Integral SCSI controller 0: Version QL12160, low voltage differential
  Disk drive: unit 1 on SCSI controller 0
Integral SCSI controller 1: Version QL12160, low voltage differential
IOC3/IOC4 serial port: tty3
IOC3/IOC4 serial port: tty4
IOC3/IOC4 serial port: tty5
IOC3/IOC4 serial port: tty6
Gigabit Ethernet: eg0, module 001c02, slot -1, firmware version 12.4.10
Integral Gigabit Ethernet: tg0, module 001c01, PCI bus 1 slot 4
IOC3/IOC4 external interrupts: 1
USB controller: type OHCI
USB controller: type OHCI
HUALALAI 2# topology

Machine HUALALAI has:
8 cpu's
2 memory nodes

The cpus are:
cpu 0 is /hw/module/001c01/node/cpubus/0/a
cpu 1 is /hw/module/001c01/node/cpubus/0/b
cpu 2 is /hw/module/001c01/node/cpubus/1/a
cpu 3 is /hw/module/001c01/node/cpubus/1/b
cpu 4 is /hw/module/001c02/node/cpubus/0/a
cpu 5 is /hw/module/001c02/node/cpubus/0/b
cpu 6 is /hw/module/001c02/node/cpubus/1/a
cpu 7 is /hw/module/001c02/node/cpubus/1/b

The nodes are:
node 0 is /hw/module/001c01/node
node 1 is /hw/module/001c02/node

The topology is defined by:
/hw/module/001c01/node/link -> /hw/module/001c02/node
/hw/module/001c02/node/link -> /hw/module/001c01/node

/hw/module/001c01/node/xtalk/0/link -> /hw/module/001c01/IXbrick
/hw/module/001c02/node/xtalk/0/link -> /hw/module/001c02/IXbrick