Power Challenge L, 12x R10000 CPUs
#1
Power Challenge L, 12x R10000 CPUs
My deskside Power Challenge L, recently revived:

Code:
everest 27# hinv -v
CPU Board at Slot 2: (Enabled)
  Processor 0 at Slot 2/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 1 at Slot 2/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 2 at Slot 2/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 3 at Slot 2/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
CPU Board at Slot 3: (Enabled)
  Processor 4 at Slot 3/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 5 at Slot 3/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 6 at Slot 3/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 7 at Slot 3/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
CPU Board at Slot 4: (Enabled)
  Processor 8 at Slot 4/Slice 0: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 9 at Slot 4/Slice 1: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 10 at Slot 4/Slice 2: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
  Processor 11 at Slot 4/Slice 3: 194 Mhz R10000 with 2 MB secondary cache (Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.6
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
Secondary unified instruction/data cache size: 2 Mbytes
Data cache size: 32 Kbytes
Instruction cache size: 32 Kbytes
Main memory size: 2048 Mbytes, 2-way interleaved
MC3 Memory Board at Slot 1: 2048 MB of memory (Enabled)
  Bank A contains 64 MB SIMMS (Enabled)
  Bank B contains 64 MB SIMMS (Enabled)
  Bank C contains 64 MB SIMMS (Enabled)
  Bank D contains 64 MB SIMMS (Enabled)
  Bank E contains 64 MB SIMMS (Enabled)
  Bank F contains 64 MB SIMMS (Enabled)
  Bank G contains 64 MB SIMMS (Enabled)
  Bank H contains 64 MB SIMMS (Enabled)
I/O board, Ebus slot 5: IO4 revision 1
Integral EPC serial ports: 4
Integral Ethernet controller: et0, Ebus slot 5
FDDIXPress controller: ipg0, version 1
EPC external interrupts
Integral SCSI controller 4: Version WD33C95A, differential, revision 1
Integral SCSI controller 3: Version WD33C95A, differential, revision 1
Integral SCSI controller 2: Version WD33C95A, differential, revision 1
Integral SCSI controller 1: Version WD33C95A, single ended, revision 0
  Disk drive: unit 1 on SCSI controller 1
Integral SCSI controller 0: Version WD33C95A, single ended, revision 0
CC synchronization join counter
Integral EPC parallel port: Ebus slot 5
VME bus: adapter 0 mapped to adapter 21
VME bus: adapter 21

everest 28# uname -a
IRIX64 everest 6.2 03131016 IP25

everest 29# diskpatch -v
sc1d1l0:  Disk         SEAGATE ST336754LW      0003  Serial: 3KQ1M59V

Inside, left to right: MC3, 3x IP25, IO4, V/FDDI:

[Image: IMG_7310_sm.JPG]

The IO4 is fitted with a dual 1Gb/s FCAL mezzanine, and a triple channel SCSI mezzanine. There's also an Interphase VME FDDI board installed.

This system recently had some power problems, but I managed to fix them. The beast is back  Cool
(This post was last modified: 12-07-2021, 12:53 PM by jan-jaap.)
jan-jaap
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12-06-2021, 10:44 PM


Messages In This Thread
Power Challenge L, 12x R10000 CPUs - by jan-jaap - 12-06-2021, 10:44 PM
RE: Power Challenge L, 12x R10000 CPUs - by Irinikus - 12-07-2021, 03:25 PM
RE: Power Challenge L, 12x R10000 CPUs - by jpstewart - 12-08-2021, 01:07 AM
RE: Power Challenge L, 12x R10000 CPUs - by jan-jaap - 12-08-2021, 10:01 AM

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