[robespierre]

MIPSIV (the R10000) and MIPS64 (Octeon) are not completely compatible. Cache control is incompatible, IIRC. So what may be happening is that the cache is in an inconsistent state, explaining your bus errors (bus errors are detected external to the CPU and sometimes reflect bogus addresses). The segmentation violations are detected by the CPU when it accesses a process's page tables in response to a TLB miss. Stale cache data could also cause those.
Take a look at the 2nd edition of "See MIPS Run" and what it says about the differences.

The output is hard to understand because there is no indication of which processes are being killed but we know they are being run from rc files.
Some other output stands out, in particular the usage notes indicate that something is wrong with the parameters being supplied to those utilities in the rc files. Also "unexpected !=" means there is a syntax error, possibly caused by an unset variable.
You can copy and paste one line at a time from the rc file to see where the problem first occurs.