[jwhat]

Hi Weblacky,

yes agree that the boot strap process will load the PROM into memory and execute from there.

But the CPU Speed configuration is persistent, so "flash" program is updating the EEPROM.

While we can poke stuff into memory, any such change will not be persistent across boots.

I have a copy of the "See MIPS Run" book and it has details on the "MIPS CPU Control Registers" and there is nothing there that relates to CPU Speed Control.

CPU Speed is managed via external clock in systems of this era, I would have thought (unlike current Intel and other CPUs which have variable speed based on load/battery level etc).

This is is why I am wondering how speed is managed.

If the speed is encoded as data in the PROM then it implies there is some software control mechanism ocurring...

First something is loading the data, as part of PROM code (that would have to be the main CPU) and then based on that it is sending some control request to clock to ensure it runs at the correct speed.

Hence my speculation on starting at one speed and then changing speed based on data value.

Is the CPU clock a seperate chip on the PIMM board ?

I guess the alternative is that the data in PROM is just used for internal calculations and reporting use and does not have any role in actual control of clock. In this case the "flash" process also "sticks" some data somewhere else which is used to control Clock speed.

Given that there are POD/CAC instructions to read/write to PROM and that is where the speed data is I will think you can use these.

We just need to get syntax right, starting with reading first ;-)

But it is easy for me to see what is reported from RAM ...

I will do some further testing on weekend.

As electronics person, could you look at PIMM for the CPU clock chip ?

Cheers from Oz,


jwhat/John.