[vishnu]

Great look at SGI's PMAP chips; they provided a hardware implementation of mapping between physical memory (RAM) and virtual memory (typically on the disk(s), commonly referred to as swap). As a side note, when a lot of memory was swapped it could lead to the unwelcome phenomenon known as thrashing, where the OS is constantly moving chunks of memory from swap space into physical RAM.

[jan-jaap]

I think in this case PMAP is a little different. This is halfway the graphics pipeline, virtual memory isn't used here

It's not too complicated to recognize the blocks in the Graphics Architecture diagram in the DE3 PCB:

The XBAR (crossbar) are probably the fat interconnect dots between the image planes and the MGP (Multimode Graphics Processor)
The system does not have enough VRAM to have a 1280x1024 RGB frame buffer. Your application doesn't need to run in RGB mode either. The image planes can contain indexed color data. If it's RGB itgoes straight to the DACs, if it isn't it must pass through a color map lookup table.

IMHO, the PMAP probably integrates the MGP and the color map. It might be sort for MGP-colorMAP

NB: the Window Planes should have been inside the green area. The DE3 has space for 20 VRAM SIMMs, you can see 15 are filled in this one.
5 SIMMs make up an 8-plane increment.
You always need 4 planes for window ID and 4 planes overlays/underlays. These make up 1 bank of 5 SIMMs.
This system has two more banks filled, so it has 16 usable bitplanes. If you scroll back this thread you can see this confirmed in the terminal window with 'hinv' and 'gfxinfo'.
If this system had the last bank filled as well, it would have 24 (usable) bitplanes. You could use this for an RGB visual. But not too fast: if you want double buffering you'll have to split your 24 planes into two 12-bit indexed visuals.

Similarly, with 16 bitplanes I could run 8 bit, dual buffered.

[arhiman57]

Thanks for this great deep dive of ressurecting this baby, so much usefull information, high end debug

If I understand correctly, It seems that this machine is the lowest possible Professional Series config ? (not the realiest due to 4D/60)

We don't really know the availabilioty date of the 4D/50, maybe fall 1987 (after 11/87 4D/70 annoucement ?), so if this system was delivered around spring 88, it will be very close to Clover2, and not so far from PI and Power Series as you say before. Maybe an additionnal discount was made, and if the system was focused on dev and no high end visualization, this config make maybe sense.

PS : i Found in comp.sys.Sgi that a person bought a new 4D/60 "single board set" in 11/87

[vishnu]

There's a timeline on the SGI wikipedia page, I think it's at least pretty close to accurate, link:

https://en.wikipedia.org/wiki/Silicon_Graphics

[jan-jaap]

If you piece together history based on magazine articles and announcements, then the 4D/60 was showed first at the March '87 NCGA conference and exhibition. In July they were shipping to customers, but that same month the turbo upgrade for 4D/60 owners (4D/60T) was announced. This single board computer with the new 12.5MHz CPU is better known as the IP4. In October '87 they started shipping the 4D/70 which came from factory with the IP4. In April '88, the price-reduced 4D/50 was announced.

The initial price for a 4D/60 was $74500. The price for the turbo upgrade was $7500. When the 4D/70 started shipping, the price was again $74900 and the price of the 4D/60 was simply dropped by $7500. The initial price for a 4D/50 was $49900.

If you add all of this up, if gives a good idea of your chances of finding an unmolested 4D/60. First of all, it was only a couple of months between initial shipment and the arrival of the IP4 so they probably went to select customers. The opportunity to get a 2 .. 3x speed improvement for an extra 10% was probably irresistible for 4D/60 owners. I doubt many 4D/60s were sold once the 4D/70 started shipping, and the arrival of the 4D/50 surely was the end of the 4D/60.

So a time window of a couple of months, select (government?) customers and an irresistible upgrade. You do the math

---

The metal chassis of this 4D/50 'G' has a sicker on it that says "SBC CHASSIS REV H, DATE 5/25/88", so it was probably delivered to customer in Q3 '88.

[robespierre]

Have you seen this marketing summary?

INTRODUCTION

This specification describes the RISC-based, high performance, IRIS 4D/70 workstation integrated and manufactured by Silicon Graphics Inc.

For the purposes of this specification the term "workstation" is defined as comprising any and all integrated and configured devices that form a user operable system environment.

REFERENCE DOCUMENTATION
U.S./Domestic Standards

UL-478 - Standard for Safety-EDP Units and Systems
FCC - Regulatory Docket #20780, Part 15, Subchapter J-Class A
CSA - Standard C22.2, No. 154- Safety of Data Processing Systems
ESDI - Preliminary ANSI Working Document Number X3T9.3/86 Revision 1.0 10/20/86
VMEbus Specification, Revision C.1, dated October 1985

European Standards

IEC - Standard 380 - Safety of Office Machines
VDE - Standard 0806 - Safety of Office Machines
VDE - Standard 0871 - Suppression of REI. (Level A compliance required.)
ZH-1 - Standard 618 - Safety Regulations for Display Work Places in the Office Sector

CONFIGURATION SUMMARY

Base Configuration

12-slot twin tower enclosure with power supply, cabling, I/O panel, status panel, 115 VAC power module and cooling

IP4 PCA with 12.5 MHz RISC CPU and Floating Point Coprocessor, and 8 MB of parity memory

170 MB SCSI or 380 MByte ESDI disk with controller

Ethernet PCA

GF3 PCA with 17 Geometry Engines and 4 Geometry Accelerators (all at 10 MHz)

DE2 PCA with 12 user-accessible bit planes

TB2 PCA with twelve-bit-color pixel mapping resource

19" Color Monitor

101 Key full function keyboard

3-Button serial Mouse

Shipping containers

8.3.4 CROSSBAR Custom Chip

There are five (5) pairs of CROSSBAR and PIXELMAP chips in the Workstation graphics subsystem. The CROSSBAR chip allows the graphics subsystem to switch between 3 color models of pixel value representation on a pixel by pixel basis. A graphic cursor is supported by the CROSSBAR via an on-chip SRAM memory. The memory allows a maximum cursor size of 32x32x3, 32x64x1 or 64x32x1 to be displayed with size and positioning determined by software selectable, on-chip registers. The CROSSBAR also supports a ful-screen crosshair style cursor.

8.3.5 PIXELMAP Custom Chip

The PIXELMAP accomplishes the pixel representation mapping by providing a 64x28 bit auxiliary color look-up table for overlays and underlays with flexible auxiliary color selection logic.

The CROSSBAR and PIXELMAP are loaded from the graphics manager (68020) of the GF3 host interface.

8.4 Twelve-Bit Color Map (TB2)

The TB2 board offers a 12-bit color map scheme. The TB2 has no separate hue and intensity mapping. The TB2 communicates with the DE3 color maps loaded from the GF3. The PMAP outputs on the DE3 are carried to the TB2 via an on-board 200-pin connector.

The TB2 provides for a 12-bit in/24-bit out color resource capable of displaying up to 4096 colors from a palette of 16.7 million in one map mode. The TB2 presents fifteen independent maps each with a maximum of 238 RGB entries in a multi-map mode. One of these 238 entry maps is an identity map, allowing RGB. Another map can be configured to do gamma-corrected RGB.

8.4.2 FDAC

The FDAC comprises three custom high speed 8-bit digital-to-analog converters with video controls and 3:1 multiplexer. The FDAC data
conversion dates are capable of maintaining a 123 Mhz video rate required to support the display of 1280 x 1024 bits of information in a 60 Hz non-interlaced manner.
The FDAC output is capable of driving doubly-terminated 75-ohm coaxial cable a distance of 15 feet minimum without external buffering.

8.5 Graphics Options

8.5.1 Z-Buffer (ZB2) Board

The ZB2 provides hardware assistance for hidden surface removal in 3D.
The ZB2 board interfaces to the GF3 and DE3 board via the graphics bus of P2 and P3 connectors.

8.5.2 Genlock (CG2)

The Genlock board option has interfaces to the applications processors, TB2, DE3, and the I/O panel. It gets its power from the system backplane.

When CG2 is installed, workstation internal video/image generation can be synchronized (CG2 supplies master video clock to TB2) with an external video signal via a "remote source in" input connector mounted on the I/O panel of the workstation. The feature will allow for video image blending and overlay of workstation generated images with composite NTSC images from other workstations or video generators such as TV cameras and VCRs.

A second function of the CG2 provides NTSC compatible video output for recording via a VCR or other device. The NTSC output of the CG2 deviates from "broadcast" NTSC.

In general, R, G, and B color triplet information from the workstation display engine (DE) is converted to Y (luminance), R - Y, and B - Y color information and then modulated on a 3.58 Mhz color subcarrier to produce NTSC (RS-170A) color video output.

The NTSC produced by the CG2 differs from broadcast NTSC in two ways; 1) color reference angles are R-Y and B-Y instead of I and Q; and 2) spectral (color range) information.

The CG2 combines R-Y and B-Y components and then bandwidth limits the sum to 0.3 Mhz in order to minimize the delay circuitry (Y component only) required to meet broadcast spec's; i.e. bandwidth limit I to 1.3 Mhz, Q to 0.3 Mhz, delay Y and Q to maintain their relation to I, and then add them together. This means that there will be 1.0 Mhz less spectral color information in the CG2 video than that of true NTSC video.

True broadcast NTSC video may be achieved through the use of an external NTSC encoder in conjunction with the CG2 board option. (No external Genlock (clock generator) device is required since the function is contained on the CG2 board.)

8.6 Ethernet

The Ethernet controller board is standard with the base configuration and conforms to Ethernet 1.0/3.0 (IEEE 802.3).

8.7 Disk Subsystem

The workstation configuration includes one 5 1/4-inch SCSI 170 MByte or ESDI 380 MByte Winchester disk drive. The disk module includes a cooling fan and is designed to allow for simple installation/removal of the disk.

The ESDI disk subsystem includes one Interphase model #V/ESDI-3201 controller in the VME chassis. This controller can support up to two 5 1/4" form factor ESDI disk drives, and 32-bit data transfers and 32-bit addresses on the VME-bus. Additional disk drives require the addition of another ESDI controller.

The Turbo Option processor subsystem also supports an interface to SCSI peripheral devices. An optional 170 MB SCSI Winchester disk drive is available for the system.

8.8 Tape Subsystem

This option includes one 5 1/4" form factor tape drive which supports a 45 or 60 MByte cartridge, has a SCSI interface and an attached cooling fan.

8.9 Monitor

The monitor is a 19" diagonal, high resolution, color CRT display. Monitor resolution is 1280 pixels horizontal by 1024 lines vertical. Horizontal scan rate is 64 Khz. Package includes a tilt/swivel mechanism and anti-reflective coated faceplate.

8.10 Keyboard

101 Key Keyboard with 7 LEDs.

8.11 Mouse

The mouse input device has three buttons, and employs optical technology, operating over a 9.00" x 7.75" grid plate with 200 lpi resolution and RS-423 serial communication interface.

Interestingly, it keeps the "Turbo Option" descriptor, even though as far as I'm aware, all 4D/50 and 4D/70 came with the IP4 which has an on-board SCSI channel.
An unusual amount of hardware is simply for colormapping: both the PMAP chips and the TB2 have independent color maps.

[vishnu]

SGI was way out in front of the workstation market with 12 bit color (4096 colors). In the modern era, 32 bit is the norm (4,294,967,296 colors). And I'm sure all our eyes are acute enough to distinguish between each one... 

[jan-jaap]

Have you seen this marketing summary?
[...]
Interestingly, it keeps the "Turbo Option" descriptor, even though as far as I'm aware, all 4D/50 and 4D/70 came with the IP4 which has an on-board SCSI channel.
An unusual amount of hardware is simply for colormapping: both the PMAP chips and the TB2 have independent color maps.

I had not seen this, thanks.

4D/50 and 4D/70 both came with IP4. Unlike the R2300 MBC used in the 4D/60, the IP4 had SCSI. What I find somewhat surprising is that this marketing document claims that the 4D/70 would have an ESDI controller and disk, but a SCSI tape drive. I can see why a 4D/60 upgraded with an IP4 would have kept it's ESDI controller and disk, but why would you ship a 4D/70 with ESDI disk and SCSI tape? Perhaps SCSI support was limited in early IP4 PROMs and/or IRIX versions? My 4D/50 has 4D1-2.1 PROMs and supports SCSI though.

My other Professional IRIS, a 4D/70 GT, was also all SCSI based. It has the ESDI ports on the bulkhead but they're not connected and neatly organized with tiewraps to avoid anything ending up in the fan tray, I assume.

This is also why I'm fairly sure this system, the 4D/50, originally did not have ethernet: the connector is on the bulkhead, but the flatcable was neatly organized with tiewraps with the (also unused) ESDI wiring. Yet this is contradicted by this document which claims all 4D/70's came with ethernet. Perhaps "no network" was an option for high security environments?

Another mystery I've not been able to unravel yet: the chassis. The main tower of this system has a sticker that says it's "013-0101-004, SBC CHASSIS REV H, 05/25/88". First of all, if there's an SBC chassis this implies there must have been an MBC chassis. IP4 was the single board successor to the MIPS R2300 MBC. "This Old SGI" analyzes the backplane of the Professional IRIS and how it's divided in 3 sections. First 4 slots for the MBC, then 3 slots for VME options and finally 5 graphics slots. All 12 slots carry the VME P1 and P2b signals, but the graphics slots bus the P2 and P3 connectors to form a graphics bus. The first 4 slots bus P2ac, probably this is the memory bus between the R2300 CPU board and up to three R2350 memory boards with 4MB RAM each. My backplane follows this division as well so I assume it should be possible to install an R2300 MBC set if I ever found one.

So far I had imagined that perhaps the addition of SCSI would have been the difference between an MBC and an SBC chassis. The MBC used an ESDI controller and external wiring to the ESDI disk modules. It used a VME QIC-02 controller for the tape drive, again with external wiring I assume. The IP4 routes SCSI via P3. Would the MBC chassis have lacked SCSI routing to the drive tower? OTOH, considering the short time between the 4D/60 and the 4D/70, they must have been working on IP4 before the 4D/60 was released. Same for the graphics: 5 slots were reserved for graphics, but CLOVER1 is never more than 4. CLOVER2 ("GT") is always 5. Questions...

   

The Hardware Developer Handbook also differs from the layout as reverse engineered by "This Old SGI":

• The Handbook doesn't even mention the MBC. The CPU is in slot 1, the ethernet VME option card is in slot 2, not 5. That itself is not incorrect because the VME32 pins are bussed across all of the slots.
  
• It says the DE/GF/TB cards are in slots 9, 10 and 11, and slot 12 for the optional ZB. That's not even possible, because the DE and TB boards are connected at the front so the GF cannot be inbetween. In my case I has GF in slot 10, DE in slot 11 and TB in slot 12. Gerhard Lenerz puts them there too, with the optional ZB in slot 9. That actually makes sense, because if you add a ZB to a system and you had to move the GF, you'd need to change VME IACK/BG jumpers on the backplane. Inconvenient.
  

I guess it's safe to say the Professional IRIS was obsolete and largely forgotten by the time the Hardware Developer Handbook was written...

I think a more realistic slot assignment for the Clover1 TwinTowers would be:

   

[vishnu]

Another graphic, for funzies:

   

[arhiman57]

I guess it's safe to say the Professional IRIS was obsolete and largely forgotten by the time the Hardware Developer Handbook was written...

You're totally right, the rev 1.0 came back in 1994 if I remember correctly. Even earlier, in 1991/1992 (compared to 1996 fro the this old sgi faq...), on comp.sys.Sgi, some question were not answered on nor totally by official  SGI tech support about early Professional Iris spares parts, upgrade path, OS support etc. And you can find many comments "these systems are very old and obsolete right now". So it's definitively not impossible that they make some mistakes  (the fact that a book like that exist is also crazy...)

As you say, the time frame between each upgrade, new series is so short back in 87/88...