Re: Your hinv's (Post them here:) -
Irinikus - 07-08-2018
<QUOTE author="Birchwood" post_id="1333" time="1530646718" user_id="253">
Birchwood post_id=1333 time=1530646718 user_id=253 Wrote:I bought <URL url="https://www.ebay.com/itm/Top-SGI-Silicon-graghic-Iris-Indigo-/263424706639?_trksid=p2047675.l2557&ssPageName=STRK%3AMEBIDX%3AIT&nma=true&si=BQgc5JMsuwS5h1Bz5GGybb4Y4mc%253D&orig_cvip=true&rt=nc">this 4K IRIS Indigo from eBay back in January, but I actually haven't got it to work until just a few weeks ago. It is my first SGI 
iris.jpeg
Both the CPU board and HD was dead on arrival, but the plastics were almost perfect. Just two small scuff marks on the front at the left side of the speaker grill that might be possible to remove. Not to mention the front door is fully intact. Anyways, bought a new HD and CPU board from Ian Mapelson. And a 4400 CPU. And 256 MB RAM... Elan gfx board... I have easily upgraded it for the same amount I bought it for 
1416.jpg
Very nice clean machine, now all you need is that Elan door to complete her! (if you can get your hands on the correct font, you could always get the Elan logo silkscreened onto your machines's existing door.)
<QUOTE author="biigD" post_id="1393" time="1531000396" user_id="261">
biigD post_id=1393 time=1531000396 user_id=261 Wrote:Code:
Indigo2 1% hinv -v
FPU: MIPS R8010 Floating Point Chip Revision: 0.1
CPU: MIPS R8000 Processor Chip Revision: 2.2
1 75 MHZ IP26 Processor
Main memory size: 256 Mbytes
Secondary unified instruction/data cache size: 2 Mbytes
Instruction cache size: 16 Kbytes
Data cache size: 16 Kbytes
Integral SCSI controller 0: Version WD33C93B, revision D
Disk drive: unit 1 on SCSI controller 0
Tape drive: unit 2 on SCSI controller 0: DAT
Integral SCSI controller 1: Version WD33C93B, revision D
On-board serial ports: 2
On-board bi-directional parallel port
Graphics board: GU1-Extreme
Integral Ethernet: ec0, version 1
Iris Audio Processor: version A2 revision 1.1.0
EISA bus: adapter 0
Code:
Indigo2 3% /usr/gfx/gfxinfo
Graphics board 0 is "GR2" graphics.
Managed (":0.0") 1280x1024
8 GEs, 2 REs, 24 bitplanes, 4 auxplanes, 4 cidplanes, Z-buffer
GR2 revision 6, VB2.0
HQ2.1 rev A, GE7 rev B, RE3.1 rev A, VC1 rev B, MC rev D
unknown, assuming 19" monitor
Video board revision 3
Very cool RARE configuration, I love the 777 poster buy the way!
Re: Your hinv's (Post them here:) -
biigD - 07-10-2018
Thanks Irinikus!
I moved to New York City a couple years back and needed to thin my SGI collection for the smaller living space. The 777 poster made it natural to select a teal Indigo2 as my IRIX machine of choice.
I’ve been really happy with it - nobody is going to mistake the thing for an Octane, but it’s surprisingly responsive for a 75 MHz machine.
Re: Your hinv's (Post them here:) -
Jacques - 07-11-2018
<QUOTE author="biigD" post_id="1393" time="1531000396" user_id="261">
biigD post_id=1393 time=1531000396 user_id=261 Wrote:Code:
Indigo2 1% hinv -v
FPU: MIPS R8010 Floating Point Chip Revision: 0.1
CPU: MIPS R8000 Processor Chip Revision: 2.2
1 75 MHZ IP26 Processor
Main memory size: 256 Mbytes
Secondary unified instruction/data cache size: 2 Mbytes
Instruction cache size: 16 Kbytes
Data cache size: 16 Kbytes
Integral SCSI controller 0: Version WD33C93B, revision D
Disk drive: unit 1 on SCSI controller 0
Tape drive: unit 2 on SCSI controller 0: DAT
Integral SCSI controller 1: Version WD33C93B, revision D
On-board serial ports: 2
On-board bi-directional parallel port
Graphics board: GU1-Extreme
Integral Ethernet: ec0, version 1
Iris Audio Processor: version A2 revision 1.1.0
EISA bus: adapter 0
Code:
Indigo2 3% /usr/gfx/gfxinfo
Graphics board 0 is "GR2" graphics.
Managed (":0.0") 1280x1024
8 GEs, 2 REs, 24 bitplanes, 4 auxplanes, 4 cidplanes, Z-buffer
GR2 revision 6, VB2.0
HQ2.1 rev A, GE7 rev B, RE3.1 rev A, VC1 rev B, MC rev D
unknown, assuming 19" monitor
Video board revision 3
Lovely BigD! Cracking setup.
Re: Your hinv's (Post them here:) -
jan-jaap - 07-13-2018
<QUOTE author="Irinikus" post_id="1402" time="1531046292" user_id="62">
Irinikus post_id=1402 time=1531046292 user_id=62 Wrote:Very nice clean machine, now all you need is that Elan door to complete her! (if you can get your hands on the correct font, you could always get the Elan logo silkscreened onto your machines's existing door.)
Not necessarily ... the "Elan silkscreen door" goes with an R3000 Elan Indigo. The R4x00 Elan Indigo had a standard (blank?) door and an "Elan" badge.
The devil is in the details
Re: Your hinv's (Post them here:) -
Irinikus - 07-14-2018
<QUOTE author="jan-jaap" post_id="1494" time="1531516042" user_id="183">
jan-jaap post_id=1494 time=1531516042 user_id=183 Wrote:Not necessarily ... the "Elan silkscreen door" goes with an R3000 Elan Indigo. The R4x00 Elan Indigo had a standard (blank?) door and an "Elan" badge.
The devil is in the details 
Thanks for alerting me about this

(Something to look out for.)
The only problem for those of us who don’t already have one, is that these badges must be super rare by now!
Re: Your hinv's (Post them here:) -
LarBob - 07-16-2018
Moved my hinvs
here!
Re: Your hinv's (Post them here:) - CiaoTime - 08-12-2018
Starting it off with something a little interesting. Apologies for the brutal image quality, heh.
<IMG src="https://cdn.discordapp.com/attachments/324337193122267137/470334932263370752/20180720_222333.jpg">[img]<URL url="https://cdn.discordapp.com/attachments/324337193122267137/470334932263370752/20180720_222333.jpg"><LINK_TEXT text="https://cdn.discordapp.com/attachments/ ... 222333.jpg">https://cdn.discordapp.com/attachments/324337193122267137/470334932263370752/20180720_222333.jpg</LINK_TEXT>[/img]</IMG>
Two Origin 200 GigaChannels linked together over CrayLink and XIO!
Re: Your hinv's (Post them here:) -
netfreak - 08-25-2018
I like the Indy as a basic IRIX workstation. Runs silent with the Sony PSU most of the time.
Code:
CPU: MIPS R5000 Processor Chip Revision: 1.0
FPU: MIPS R5000 Floating Point Coprocessor Revision: 1.0
1 180 MHZ IP22 Processor
Main memory size: 256 Mbytes
Secondary unified instruction/data cache size: 512 Kbytes on Processor 0
Instruction cache size: 32 Kbytes
Data cache size: 32 Kbytes
Integral SCSI controller 0: Version WD33C93B, revision D
Disk drive: unit 1 on SCSI controller 0 (unit 1)
On-board serial ports: 2
On-board bi-directional parallel port
Graphics board: Indy 24-bit
Integral Ethernet: ec0, version 1
Integral ISDN: Basic Rate Interface unit 0, revision 1.0
Iris Audio Processor: version A2 revision 4.1.0
Vino video: unit 0, revision 0, IndyCam not connected
Code:
Graphics board 0 is "NG1" graphics.
Managed (":0.0") 1280x1024
24 bitplanes, NG1 revision 3, REX3 revision B, VC2 revision A
MC revision C, xmap9 revision A, cmap revision C, bt445 revision A
Display 1280x1024 @ 72Hz, monitor id 15
RE: Your hinv's (Post them here:) -
bjornl - 10-07-2018
Here's my Origin 2000 with 64 cpus, which I think is maximum cpu count without special router.
I spend some time in putting stuff together that I have been collecting for a long time, and clean up at the same time

The result was a couple of Origin 2000 and Onyx 2 racks, and I managed to connect the cpu racks together into one 64 cpu system.
I have more memory to put in, but not more directory memory that is required for >32 cpus. If anyone has directory memory for sale I might be interested.
I estimate power consumption close to 5600W (1400W x 4) and it is running on a 220V , 3x16A.
What software can I run to stresstest this

?
The setup is not so visually pleasing because of the limited space I have in my garage, but some picture are always nice.
I think the hinv is unecessary long. Because there are different types of cpus in the system the list each cpu as a separate line.
It is strange they just couldn't make it report
Code:
32 250 MHZ IP27 Processors
32 400 MHZ IP27 Processors
So, here is the complete hinv as well
Code:
universe 1# hinv
Processor 0: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 1: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 2: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 3: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 4: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 5: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 6: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 7: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 8: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 9: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 10: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 11: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 12: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 13: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 14: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 15: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 16: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 17: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 18: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 19: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 20: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 21: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 22: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 23: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 24: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 25: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 26: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 27: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 28: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 29: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 30: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 31: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 32: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 33: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 34: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 35: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 36: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 37: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 38: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 39: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 40: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 41: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 42: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 43: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 44: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 45: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 46: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 47: 250 MHZ IP27
CPU: MIPS R10000 Processor Chip Revision: 3.4
FPU: MIPS R10010 Floating Point Chip Revision: 3.4
Processor 48: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 49: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 50: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 51: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 52: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 53: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 54: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 55: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 56: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 57: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 58: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 59: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 60: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 61: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 62: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Processor 63: 400 MHZ IP27
CPU: MIPS R12000 Processor Chip Revision: 3.5
FPU: MIPS R12010 Floating Point Chip Revision: 3.5
Main memory size: 17408 Mbytes
Instruction cache size: 32 Kbytes
Data cache size: 32 Kbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 4 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Secondary unified instruction/data cache size: 8 Mbytes
Integral SCSI controller 44: Version QL1040B (rev. 2), single ended
Disk drive: unit 4 on SCSI controller 44
Disk drive: unit 5 on SCSI controller 44
CDROM: unit 6 on SCSI controller 44
Integral SCSI controller 34: Version QL1040B (rev. 2), single ended
Disk drive: unit 1 on SCSI controller 34
Disk drive: unit 2 on SCSI controller 34
Disk drive: unit 3 on SCSI controller 34
Disk drive: unit 5 on SCSI controller 34
Integral SCSI controller 0: Version QL1040B, single ended
Disk drive: unit 1 on SCSI controller 0
Disk drive: unit 4 on SCSI controller 0
CDROM: unit 6 on SCSI controller 0
Integral SCSI controller 10: Version QL1040B (rev. 2), single ended
CDROM: unit 6 on SCSI controller 10
Integral SCSI controller 12: Version QL1040B, single ended
CDROM: unit 6 on SCSI controller 12
Integral SCSI controller 36: Version QL1040B (rev. 2), single ended
Integral SCSI controller 14: Version QL1040B (rev. 2), single ended
CDROM: unit 6 on SCSI controller 14
Integral SCSI controller 28: Version QL1040B (rev. 2), single ended
Integral SCSI controller 29: Version QL1040B (rev. 2), single ended
Integral SCSI controller 37: Version QL1040B (rev. 2), single ended
Integral SCSI controller 13: Version QL1040B, single ended
Integral SCSI controller 35: Version QL1040B (rev. 2), single ended
Integral SCSI controller 1: Version QL1040B, single ended
Integral SCSI controller 11: Version QL1040B (rev. 2), single ended
Integral SCSI controller 45: Version QL1040B (rev. 2), single ended
Integral SCSI controller 15: Version QL1040B (rev. 2), single ended
Integral SCSI controller 30: Version QL1040B (rev. 2), differential
Integral SCSI controller 33: Version QL1040B (rev. 2), differential
Integral SCSI controller 31: Version QL1040B (rev. 2), differential
Integral SCSI controller 32: Version QL1040B (rev. 2), differential
IOC3/IOC4 serial port: tty48
IOC3/IOC4 serial port: tty15
IOC3/IOC4 serial port: tty1
IOC3/IOC4 serial port: tty2
IOC3/IOC4 serial port: tty47
IOC3/IOC4 serial port: tty33
IOC3/IOC4 serial port: tty34
IOC3/IOC4 serial port: tty13
IOC3/IOC4 serial port: tty11
IOC3/IOC4 serial port: tty12
IOC3/IOC4 serial port: tty14
IOC3/IOC4 serial port: tty16
IOC3/IOC4 serial port: tty36
IOC3/IOC4 serial port: tty35
IOC3/IOC4 serial port: tty30
IOC3/IOC4 serial port: tty29
Gigabit Ethernet: eg1, module 5, XIO slot io10, firmware version 0.0.0
Fast Ethernet: ef14, version 1, module 6, slot io1, pci 2
Integral Fast Ethernet: ef0, version 1, module 1, slot io1, pci 2
Fast Ethernet: ef20, version 1, module 5, slot io1, pci 2
Fast Ethernet: ef5, version 1, module 2, slot io1, pci 2
Fast Ethernet: ef6, version 1, module 3, slot io1, pci 2
Fast Ethernet: ef7, version 1, module 4, slot io1, pci 2
Fast Ethernet: ef15, version 1, module 7, slot io1, pci 2
Gigabit Ethernet: eg0, module 7, XIO slot io5, firmware version 0.0.0
Fast Ethernet: ef13, version 1, module 8, slot io1, pci 2
Origin BASEIO board, module 5 slot 1: Revision 4
Origin BASEIO board, module 6 slot 1: Revision 4
Origin BASEIO board, module 2 slot 1: Revision 4
Origin BASEIO board, module 1 slot 1: Revision 3
Origin BASEIO board, module 3 slot 1: Revision 3
Origin BASEIO board, module 4 slot 1: Revision 3
Origin BASEIO board, module 7 slot 1: Revision 4
Origin BASEIO board, module 8 slot 1: Revision 4
Origin MSCSI board, module 5 slot 5: Revision 4
IOC3/IOC4 external interrupts: 7
IOC3/IOC4 external interrupts: 1
IOC3/IOC4 external interrupts: 9
IOC3/IOC4 external interrupts: 2
IOC3/IOC4 external interrupts: 3
IOC3/IOC4 external interrupts: 4
IOC3/IOC4 external interrupts: 8
IOC3/IOC4 external interrupts: 6
RE: Your hinv's (Post them here:) -
uunix - 10-07-2018
bjornl .. awesome..