[fleedwood]

Going through the errors I got there is a tight pattern. I’m trying to find real documentation but only found a few for other MIPS processors.  They claim there MAY be some kind of external multiplexer to interact with the external cache (it’s not a direct track from CPU to SRAM).  Can anyone give more info on this?  Because this feels like a solder joint/bad connection or a damaged IC that performs the interaction between the CPU register signalling and the actual addressing of the external CACHE.  If so, I might find a bad IC or reflow something to see if the communication lines clear up…doesn’t seem that random…but I have no info on how the CPU couples to secondary SRAM?  Anyone know?

as I haven't seen R14k/R16k user manuals I'm not 100% sure the scache interface is the same as on R10k/R12k, but as a starting point...

Look in the R10k user manual

https://usermanual.wiki/Document/0072490001.2505313346

there is a picture how the scache is connected on page 38 and signal description on page 69/70